The present invention relates to a method and apparatus for electrical signal phase detection and a system incorporating the same.
Digital communication equipment is used in a wide variety of devices for the transmission of digital information. Such information includes numerical data in computers and digital encodings of voice in telecommunications systems.
In the course of transmission of digital signals from a transmitter to a receiver, the digital signals tend to become degraded. Degradation may involve loss of overall strength of the signal, and loss of definition of the pulse edges: at the time of sending, the pulse edges typically rise and fall sharply with respect to the overall pulse length giving a cleanly defined shape to the pulse whilst, at the receiver, the rate of rise and fall of the pulses tends to decrease resulting in less sharply defined pulses. In order to correct for these degradations, it is common practice to regenerate the original digital signal from the distorted one at the receiving end of a digital communication link. The regenerated signal may then be retransmitted along a further transmission link or be further processed locally.
To regenerate a received signal, typically, the receiver must ensure that the received data signal (the data signal) is processed synchronously relative to a local clock signal (the clock signal). It is also desirable to ensure that the data signal is not sampled near the degraded edges of the received data pulses which would lead to incorrect interpretation of the signal. Typically a phase locked loop would be used, containing a phase detector, an adjustable oscillator, and feedback circuit so that the receiver tends to a target clock-to-data phase relationship (the set point) which is not easily adjustable.
Alternatively in some circumstances a delay locked loop could be used, comprising a phase detector, a clock signal source, an adjustable delay in the clock or data path, and feedback circuit so that the receiver tends to a target clock-to-data phase relationship (the set point) which typically is not easily adjustable.
The target relationship may not be optimum, for example where the eye of the received data signal is asymmetrical.
It is known to make a compensating adjustment by means of one or more delays introduced into one or more paths leading from the clock signal or data signal to the phase detector or decision circuit. This has the disadvantage that it requires the delay circuitry to operate at the full speed of the clock or data signal, with associated hardware costs, power consumption, and crosstalk which can act to degrade the data or clock signal before it reaches the decision circuit and/or phase detector.
It is also known to add an offset in the phase locked or delay locked loop, for example by adding a voltage to the phase detector output, thereby directly affecting the loop feedback input signal. This has the disadvantages of being susceptible to pattern-dependent jitter, and operating only over a limited phase range.
A clock-to-data phase detector is a device which takes as two of its inputs a data signal and a clock signal and generates signals giving information about the phase difference between the data signal and clock signal. A known means of representing the phase difference information is by means of a pair of signals: the first signal (the phase difference signal) comprises a component which represents the phase difference and a further component which represents the variations in the number of edges occurring in the data; the second signal (the reference signal) represents only the latter variation. Subsequent subtraction of the reference signal from the phase signal gives a signal (the difference signal) representing the difference in phase.
It is known [from C. R. Hogge, xe2x80x9cA Self Correcting Clock Recovery Circuitxe2x80x9d, Journal of Lightwave Technology, Vol. LT-3, No. 6, December 1985] to generate a phase difference signal employing circuitry constructed using silicon components, whilst at the same time generating a reference signal by employing a fixed delay introduced by means of a delay line.
U.S. patent application Ser. Nos. 08/847,426 and 09/156,019 (Continuation-in-part) provide an improved method and apparatus for detecting the phase difference between a digital data signal and a clock signal. By ensuring that no pulse in the output phase signal is narrow enough to introduce a non-linearity, a source of non-linearity exhibited in previous known phase detectors is avoided. In addition, by ensuring that critical timing paths through the circuit contain similar circuit blocks, with similar propagation delays, relative time relationships are preserved from clock and data inputs to XOR inputs. The circuit is therefore largely insensitive to changes in the characteristics of the components so long as they all move together, as they would in an integrated circuit implementation.
U.S. Pat. No. 5,250,913 provides a phase detector for a phase locked loop for bit clock retrieval where the phase detector employs a plurality of variable unit delays and has a constant gain region that is a percentage of the clock period over an extended frequency range of the VCO enabling a single chip to operate for several applications at widely different frequencies.
The invention seeks to provide an improved method and apparatus for detecting the phase difference between a digital data signal and a clock signal.
According to a first aspect of the present invention there is provided a digital signal phase detector comprising: a data signal input for receiving a data signal; a clock signal input for receiving a clock signal; a set point control signal input for receiving a set point control signal indicative of a desired set point of the detector; a first circuit coupled to said data signal input and said clock signal input and arranged to provide a phase difference signal representative of both the clock period of the clock and the difference in phase between the clock and the data signal; a second circuit coupled to said data signal input and the clock signal input and arranged to provide a reference signal representative of the clock period of the clock signal; wherein at least one of said first and second circuits is coupled to said set point control signal and the corresponding output signal is representative of said set point control signal; and wherein a comparison of the phase difference signal with the reference signal provides an indication of the difference between the desired set point of the circuit and the phase difference between the clock and the data signal.
Advantageously, where the eye of the received signal is asymmetrical, the sampling point can be offset to the optimal sampling position.
Advantageously, whilst certain undesired delays may exist within a phase detector circuit or in circuitry leading to it, these can be compensated for.
Advantageously, the delay elements are arranged to act on regenerated digital signal pulses. The height and speed of such pulses are more predictable than those of the unregenerated data signal, and consequently the delay circuits work better.
Advantageously, the circuitry in the data and clock paths leading to the phase detector is minimised, thereby reducing power consumption, crosstalk, and improving overall performance.
Advantageously, the phase difference and reference signal pulses can be made to overlap whereby to reduce the data content to be filtered out of the error signal, thereby improving performance.
Preferably, the phase detector is arranged such that timing of pulse edges in said output signal of said at least one of said first and second circuits varies responsive to said set point control signal.
Preferably, said one of said first and second circuits comprises a first adjustable delay circuit coupled to said set point control signal, and arranged to introduce a signal delay responsive to said set point control signal, whereby to render the corresponding output signal of said one of said first and second circuits representative of said set point control signal.
Preferably, each of said first and second circuits comprises an adjustable delay circuit coupled to said set point control signal, and arranged to introduce a signal delay responsive to said set point control signal, whereby to render the output signal of each of said first and second circuits representative of said set point control signal.
Preferably, said adjustable delay circuits are arranged to introduce oppositely-varying delays responsive to said set point control signal.
Preferably, said one of said first and second circuits comprises a second adjustable delay circuit coupled to said set point control signal, and arranged to introduce a signal delay responsive to said set point control signal.
Preferably, said adjustable delay is arranged to introduce a delay of less than half of a clock cycle.
In one preferred embodiment, said adjustable delay receives a signal having pulse lengths greater than that of the input data signal.
Preferably, said adjustable delay receives a signal having a pulse length at least twice that of the input data signal.
Advantageously, delay elements may run slower than the line rate or line clock-rate: the pulse length to be delayed is typically twice the line pulse length, as opposed to the line pulse length if the data signal is delayed or half the pulse length if the clock signal is delayed.
Preferably the phase detector circuit comprises: a data-reduction circuit arranged to provide a reduced data signal which changes state upon receipt of either only rising or only falling state transitions in a digital input signal; a resynchronisation circuit arranged to provide a resynchronised reduced data signal upon receipt of a clock input signal and the reduced data signal; a first shift register circuit arranged to provide a first phase-shifted resynchronised reduced data signal upon receipt of the resynchronised reduced data signal and one or more clock signals; a second shift register circuit arranged to provide a second phase-shifted resynchronised reduced data signal upon receipt of the first phase-shifted resynchronised reduced data signal and one or more clock signals; a first Exclusive OR circuit arranged to provide a phase difference signal upon receipt of the reduced data signal and the first phase-shifted resynchronised reduced data signal; and a second Exclusive OR circuit arranged to provide a reference signal upon receipt of the resynchronised reduced data signal and the second phase-shifted resynchronised reduced data signal; an adjustable delay circuit arranged to provide a variably delayed output signal upon receipt of an input signal, responsive to a set point control signal; and wherein said adjustable delay circuit is arranged to delay one of said reduced data signal, said resynchronised reduced data signal, said first phase-shifted resynchronised reduced data signal, and said second phase-shifted resynchronised reduced data signal.
Preferably, the data-reduction circuit comprises a D-Type flip flop; the resynchronisation circuit comprises a D-Type flip flop; the first shift register circuit comprises a Latch; the second shift register circuit comprises a Latch; the first XOR circuit comprises an XOR gate; and the second XOR circuit comprises an XOR gate.
In a preferred embodiment the phase detector circuit comprises: a second adjustable delay circuit arranged to provide a variably delayed output signal upon receipt of an input signal, responsive to a set point control signal; and wherein said adjustable delay circuit and said second adjustable delay circuit are each arranged to delay a distinct one of said reduced data output signal, said resynchronised reduced data signal, said first phase-shifted resynchronised reduced data signal, and said second phase-shifted resynchronised reduced data signal.
Preferably, said adjustable delay circuit and said second adjustable delay circuits are arranged to introduce oppositely varying delays responsive to said set point control signal.
Preferably, said adjustable delay circuit is arranged to delay said reduced data signal and said second adjustable delay circuit is arranged to delay said first phase-shifted resynchronised reduced data signal.
Preferably, said first and second adjustable delay circuits are arranged to introduce oppositely varying delays responsive to said set point control signal.
According to a further aspect of the present invention there is provided a phase-locked loop circuit having a set point and comprising: a phase detector circuit according to claim 1; a loop filter and adjustable oscillator circuit arranged to provide said clock signal responsive to receipt of an output signal from said phase detector; and wherein the-set point of said phase-locked loop circuit is responsive to said set point control signal.
Preferably, said loop filter and adjustable oscillator circuit comprises: a subtractor circuit which provides a difference signal output responsive to said phase difference and reference signals; a loop filter circuit which provides a filter output signal responsive to said difference signal; an adjustable clock signal circuit which provides said clock signal responsive to said filter output signal.
According to a further aspect of the present invention there is provided a delay-locked loop data re-timing circuit comprising: a phase detector circuit according to claim 1; a decision circuit arranged to provide a re-timed data signal upon receipt of said clock signal and said data signal; and a feedback circuit arranged to receive said phase difference signal, said reference signal, and said data signal and to delay said data signal responsive to said phase difference signal and said reference signal, whereby to control the phase of said data signal prior to its delivery to said phase detector circuit and said decision circuit and to vary the set point of the phase detector.
According to a further aspect of the present invention there is provided a phase-locked loop data re-timing circuit comprising: a phase detector circuit according to claim 1; a decision circuit arranged to provide a re-timed data signal upon receipt of said clock signal and said data signal; and a feedback circuit arranged to receive said phase difference signal and said reference signal and to provide said clock signal to said phase detector circuit and said re-timing circuit responsive to said phase difference signal and said reference signal, whereby to control the phase of said clock signal prior to its delivery to said phase detector circuit and said decision circuit and to vary the set point of the phase detector.
Advantageously, the decision circuit works best if there is a time offset between the clock edges and where the actual decision point is.
Advantageously, certain undesired delays in, or leading to, the decision circuit may also be compensated for.
According to a further aspect of the present invention there is provided a system for the purposes of digital signal processing comprising a circuit according to any foregoing aspect of the present invention.
The invention is also directed to the methods by which each of the described apparatus operates and including method steps for carrying out every function of the apparatus.
According to a further aspect of the present invention there is provided a method of digital signal phase detection comprising the steps of: providing a data signal; providing a clock signal; providing a set point control signal indicative of a desired set point; providing a phase difference signal responsive to and representative of both the period of the clock signal and the difference in phase between the clock signal and the data signal; providing a reference signal responsive to and representative of the period of the clock signal; wherein at least one of said phase difference signal and reference signal is also responsive to and representative of said set point control signal; and comparing the phase difference signal with the reference signal whereby to provide an indication of the difference between the desired set point and the phase difference between the clock and the data signal.
Preferably, each of said phase difference signal and reference signal is responsive to and representative of said set point control signal.
Preferably, the signal pulse edge timing of at least one of said phase difference signal and reference signal is responsive to and representative of said set point control signal.
Preferably, timing of rising pulse edges and falling pulse edges of said at least one of said phase difference signal and reference signal varies oppositely responsive to said set point control signal.
The preferred features may be combined as appropriate, as would be apparent to a skilled person, and may be combined with any of the aspects of the invention.